Analog line generator

ABSTRACT

In an analog line generator for producing a straight line connecting two given points, which comprises an integrator, an adder and a feedback circuit from the integrator to the adder, an improvement comprising the provision of a limiter between the adder and the integrator to realize the line generation with higher accuracy and at higher speed.

United States Patent Inventors Junji Tsuda Hachioji-shi; Junzo Iwata, Hanamaki-shi; Chi Hirano, Kodairmshi, all] 011111 App]. No. 795,997 Filed Feb. 3, 1969 Patented Nov. 16, 11971 Assignees Hitachi Electronics Company Limited Kodaira-shi, Hitachi Ltd. Tokyo, Japan Priority Feb. 2, 1968 Japan 43/6005 ANALOG LINE GENERATOR 9 Ciaims, 13 Drawing Figs. ILLS. 1C1 2315/1197, 235/150.53,235/151.11, 235/183 that. Cl G063 7/20,

Primary ExaminerEugene G. Botz Assistant Examiner Felix D. Gruiber Attorney-Craig, Antone1li& Hill ABSTRACT: In an analog line generator for producing a straight line connecting two given points, which comprises an integrator, an adder and a feedback circuit from the integrator to the adder, an improvement comprising the provision of a limiter between the adder and the integrator to realize the line generation with higher accuracy and at higher speed.

ANALOG LINE GENERATOR BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an improvement of analog line generators utilizing integrators.

2. Description of the Prior Art A line generator is used not only for generating a straight line between two given points, but also as a linear approximative function generator for producing approximate curved lines on the basis of approximation of bent lines. One type of the conventional analog line generators utilizes an integrator. Such line generators have been widely used because of simplicity in construction. Nowadays, however, line generators having much higher accuracy and speed are requested, as is the case with the line-displaying technique for a display device or the electron beam generation used for the formation of IC patterns. In answer to such requests, this invention provides an improved analog line generator which has high accuracy and high operating speed.

The conventional line generators utilizing integrators are divided into two categories, one being those based on a simple integrating system which includes no feedback circuit, and the other being those including negative feedback circuit. The former has an advantage in that the constructionthereof is simple and it generates a line at a comparatively high speed, while the latter is advantageous in view of the fact that it is free from accumulation of errors and generates a straight line with high accuracy. On the other hand, the former has a disadvantage in that the error in each operation is successively accumulated, while the latters disadvantage is in the difficulty of obtaining a uniform rate (speed) of line generation.

SUMMARY OF THE INVENTION An object of this invention is to eliminate the above-mentioned disadvantage of the conventional line generator which includes an integrator with the advantage of the other type of conventional line generator which has no integrator and to provide an improved line generator which can produce accurate lines at high and uniform speed.

In order to achieve the above object, the line generator of this invention includes a limiter in the input side of the integrator, which limiter has two kinds of operating regions, one being the linear region in which the limiter operates linearly in response to input signals, and the other being the limiting region in which the limiter produces an output of predetermined fixed level regardless of the level of the input signal. Thus, the integrator receives, as an input, a signal of a fixed level until the output from the integrator reaches a value sufiiciently near to the destination point, whereby the feedback circuit is substantially disabled. Further, when the output becomes sufficiently near to the destination, the limiter is driven in the linear region with the signal corresponding to the difference between the output and the destination thereby to cause the line to converge to the destination.

Further, according to this invention, the line can be generated at a more constant speed by setting the above-mentioned fixed level according to the length of displacement between the two given points.

BRIEF DESCRIPTION OF THE DRAWINGS IF IG. 1 shows block diagrams of a conventional line generator of the feedback type;

FIG. 2 shows block diagrams for explaining the principle of the invention;

FIGS. 3a, 3b and 3c show characteristics of the limiter which is an essential Vof this invention;

FIGS. d, 5a, Eb, 6a, 6b, 6c and 7 relate to an embodiment of a circuit for setting the limiting value of the limiter; and

FIG. 8 shows an embodiment of the analog line generator of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Prior to describing the preferred embodiment of this invention, a conventional line generator will first be analyzed for better understanding of this invention.

Referring to FIG. 1 which shows basic block diagrams of the conventional line generator consisting of an x-axis unit and a y-axis unit which are identical in construction and operation thereof, reference numeral 5 indicates an integrator for the xaxis components; 6 the same for the y'axis components; and '7 and 8 indicate sign changers. Each integrator has a feedback path from the output to the input thereof. Numerals I, 2 indicate input terminals of the line generator, at which the x-axis and y-axis components of the destination signal are applied respectively, and 3, 4 indicate output terminals respectively for the x-axis and y-axis components. In a negative feedback system like this, the transfer function of the whole circuit becomes a first order function. Assuming, that the circuits are now in the steady state with inputs x and y respectively, the outputs should be x,-,,;., and y too. In this state, if signals x, and y, are suddenly applied at the input terminals 1, 2 making a steplike change in the inputs, the outputs x, y in the transient response are expressed by the following equations:

where k meat es the time constant of the circuit. In terms of x, y coordinates, the above outputs x, y indicate a straight line which is extending from the starting point P -,(x ,,y to the destination point P;(x ,y|). In terms of time, the line starts from the point P at [=0 and arrives at the point P at t= (infinite). Practically, however, the line is considered to have substantially reached the point P after a time approximately five times as long as the time constant 1/]: of the circuit. Error due to such an assumption is negligible. Thus, the time required for the line to extend from a point to another point is determined by the time constant of the circuit regardless of the distance between the two points. The fact that the time is not related to the distance, in turn, means that the generating speed of the line depends on the distance between two points. That is, the line generations of different lengths are carried out at different speeds, as they should be completed in an identical interval in spite of their different lengths. Further, the above relation between the length of the line and the generating speed holds true as to a line which is extending. That is, the generating speed of the line changes with the lapse time according to an exponential function. Such nonlinearity in the generating speed of the line presents crucial problems in the application of the line generators. For example, when such a line generator is used with a display device like a cathode-ray tube which requires response at a fast and constant speed, the intensity of the brighr spot will remarkably vary as the spot proceeds. thus making normal observation of the line difficult. Further. such a line generator cannot be used for an apparatus such as a numerical control system or an electron beam processing system in which displacement of the electron beam at constant speed is required.

The above problems have been solved by this invention, according to which the line generator includes a limiter connected to the input of the integrator, said limiter having two operating regions, the linear region signal Athe limiting region.

Referring to FIG. 2 which shows basic circuits of the analog line generator according to this invention, reference numerals 9, 10 indicate adders which add the input signal and the fedback signal; Ill, 12 the limiters; 113, M terminal for applying control signals which control the characteristics of the limiters Ill, 12. The other numerals are used to designate the same elements as those shown in FIG. ll. It will be noted that the sign changers 7, 8 are provided in the feedback circuits, whereas they are located in the input lines in FIG. Ill. This difference is not essential. The purpose of the sign changer is to apply the input signal and the fed-back signal to the integrator in the same direction. Therefore, the sign changer may be provided in the input line in case of the present invention too. The limiters l 1, 12 have operating characteristics consisting of the linear region where the output linearly varies in relation to a positive or negative minute variation of the input from the zero input state and the limiting region where an output of a constant value is produced for an input larger than the minute variation. Now, assuming that P ,.,,;1l(x,-, y,--,,,-,) is the starting point of a straight line to be generated, P,(x,, y,) the terminal point, and Ax,, Ay, componental displacements between the two points, and further assuming that the coordinates (x, y) of the straight line connecting the above two points vary according to a time function represented by Mt), x and y are expressed by the following equations.

t'M r1s'i} F yr' )+yl-1s'l From the equation (2), the generating speed of the straight line is determined by the following formula:

a a-s In order that the line-generating speed v according to the above formula (3) assumes a constant value V, the following relation should be maintained:

dx (t) V x i+ @/F Integrating both sides of the above equation (4) with the time I, Mr) will be obtained. And, MI) in the equations (2) is substituted by the thus-obtained formula as follows:

idl'i'al x Ax, All? Lx,, Ly, are expressed as function of the displacement between the Points rmlut'wm yl7El) and 100 yr) and are independent of time.

Therefore, in a steady state of the circuits shown in FIG. 2 when the respective integrators 5, 6 are producing stable outputs x,--, y,- if signals corresponding to the coordinates (x,, y of the next destination point P, are applied to the adders 9, l and concurrently signals of the limiting values Lx, and Ly, determined by the above formulas (6) are applied to the control terminals l3, 14 of the limiters ll, 12, the output from the integrator or 6) varies at a constant rate depending on the limiting value 1.x, or Ly, if Ax, or Ay, is large enough to extend into the limiting region of the limiter, and the absolute value of the input of the limiter decreases as the generated line approaches the destination point P,. When the generated line reaches the vicinity of the point P, and the input of the limiter closely approaches the limiting region, the input of the integrator assumes a value proportional to the difference between the output of the integrator and the value of the destination, and the circuit operates as a first order function to cause the output to converge to the destination correctly. The above is the operating principle of the line generator of the present invention.

Next, the operation of the circuits shown in FIG. 2 will be explained more in detail. It is assumed that a coordinate signal x representing the point P is applied to the input terminal 1 of the circuit related to the x-axis component, and that a limiting value Lx is set at the limiter 11. The whole circuit is a stable circuit provided with a feedback circuit and assumes a steady state in a certain time after initiation, when the circuit is in a balanced state with the output x from the integrator 5 being x and the input e, to the limiter 11 being zero. In this state, the x-axis component x, of the next destination point P, is applied to the input terminal I, and concurrently, the limiting value Lx, determined by the componental displacements Ax, and Ay, is set at the limiter l 1. If the linear region of limiter 11 is assumed to have widths of 60/2 in both the positive and the negative directions, the input-to-output characteristics of the limiter 11 is as shown in FIG. 3a in which the abscissa indicates the input 6, of the limiter and the ordinate the output L The limiter 11 has two operating states according to the variation of the output x of the integrator 5; that is:

l. When rx,=e eo/2 In this state, the integrator 5 is producing the output x to generate a straight line at a constant speed in response to the imposed input x,. During this period, the input of the integrator 5 (or the output L. of the limiter l1) assumes the fixed limiting value Lx, of the limiting value region as shown in FIG. 30, while the output x from the integrator 5 is varying toward x, according to the following equation:

This variation in the output corresponds to a constant rate generation of the line at the rate Lx,. The negative feedback of the output from the integrator 5 is related only to the comparison in the adder 9, but does not directly affect the input of the integrator 5. Therefore, when the line is being generated at a constant rate, the feedback can be deemed as an open loop as there exists no virtual feedback function.

As the operating state described in the above paragraph I proceeds and the output from the integrator 5 approaches x,, the input of the limiter 11 approaches the limiting value Lx, until the input falls below 60/2 whereupon the operation of the limiter is shifted in the above-mentioned linear region. This operating state may be considered as a correcting operation for bringing the output x obtained by the above operation (I) to the destination x, correctly. During this operation, the integrator 5 receives, as input, a signal proportional to the difference s, between the destination x, and the output of said integrator 5, which in turn is integrated by the integrator to become the output. The output is fed back to the input terminal through the feedback path again to become the input signal of the integrator. In this operating state. unlike in the state of the above paragraph (I), the feedback circuit establishes a closed loop to. effect the negative feedback operation. As a result, the output x of the integrator 5 is varied toward the destination .x,according to the property of the whole circuit of the first order function until it finally converges to the destination x,. As the interval of this operation corresponds to the time required for converging the minute input signal of the limiter which is smaller than (0/2 to zero in the linear region, this operation is completed in a very short time which is negligible in comparison with the whole linegenerating time. Therefore, the line can be deemed to be generated at a substantially constant rate. It is possible that the input is initially so small as to be In such case, the line is generated only by the correcting operation.

A straight line is generally produced with both x and y components of the coordinates changing; thus a straight line inclined to the coordinate axis is developed. The exception is a straight which is parallel to either x-axis or y-axis. As to a straight line parallel to the y-axis, for example, the x component of the coordinates is constant and only the y component varies. In this case, the limiting value Lx, of the limiter V, the displacements Ax, and Ay, are of negative 11 would become zero and the feedback route would be cut off, thus disabling the correcting function of the circuit. This failure of the correcting function can be prevented by the following measures. It is noted that any value other than zero can be put as the limiting value LI, because the input e of the limiter 11 is zero in this case. Therefore, the feedback path is maintained operative by setting an arbitrary constant value as the limiting value Lo, and the integrator 5 is thereby prevented from integrating the errors in the circuit.

The above explanation has been given concerning the .x-axis component of the line generation. However. it will be obvious that the same explanation applies to the y-axis component. Next, further explanation will be given relating to the limiter and the characteristics thereof.

The input-to-output characteristics of the limiter ill or 12 may be of the ordinary type having the limiting values in both positive and negative regions as shown in FIG. 3a, but is not limited to that. FIG. 3b shows the input-to-output charac teristics of a limiter which operates only in the region of positive input 6,, that is when the displacements Ax, and Ay, are of positive polarity. Such a limiter is suitable for the generation of lines having positive inclination. On the other hand, FIG. 3c shows the characteristics of a limiter which is operative when polarity. Choice of the characteristics depends on the nature of the input signal.

Referring to FIG. 4 which is a block diagram of the circuit for obtaining the limiting values Lx, and Ly, of the limiter, reference numerals 20, 21 indicate square circuits whose inputs are Ax,, Ay, respectively; '22 an adder for adding the outputs Axf" and Ayf" from the square circuits 20, 21; 23 a square root function circuit; 24 a first divider, the dividend being Ar, and the divisor being the output from the square root function circuit 23; 25 a second divider, the dividend being Ay, and the divisor being the output from the square root function circuit;

26, 2-? input terminals to which the x-axis and y-axis components Ax,, Ay, of the displacement are applied; and 28, 29 output terminal from which signals proportional to the limiting values Lx,, Ly, are obtained. It will be clear that according to the above arrangement, signals proportional to at the terminals 2 8 and 2S9 respectively. The limiting values Lx, and Ly, for the limiters 11 and 12 are obtained by multiplying the above values at the terminals 28 and29 by the constant value V.

The above-described circuit for obtaining the limiting values Lx,, Ly, for the limiters is suitable for a line generator which should have'high uniformity in the line-generating rate. However, this circuit has a disadvantage in the fact that the construction thereof is complicated. In practical use, lOO to ZOO-percent variation in the line-generating rate is usually permissible. Therefore, the formula of the limiting value may be substituted by a simpler one. Two typical examples of such simplification will be described hereunder.

The first example relates to a case where the denominator of the formulas (6) is approximated by the largerione of lAaml and lAy l; that is, the following relation is assumed:

VAxi yi-'? (l il, l i/il) Assuming ldz lildy l, then x/AanH-dy lAx l Therefore, from the equation (6),

Then, the line-generating rate v is determined as follows:

Here,

lli h 0: Ax, :1 Accordingly, V; vgw/fiv' That is, maximum change in the linegenerating rate resulting from the approximation of 1 w i yi -r a (l il, l l/il):

will bet 2 times the constant value V. This proves that the above approximation is permissible in practical operation.

Returning to the starting point of this approximation, if it is assumed that Thus, the line-generating rate v varies in a range between V and 2 V; regardless of which is the largest a diagram of the control circuit for generating control signals depending on which is the largest lAx l or [A9,],

and FIG. 5b being a diagram of the limiting-value-generating circuit which is controlled by the signal from the control circuit shown in FIG. 5a. FIGS. 60, 6b and 60 show the input-tooutput characteristics of the control circuit shown in FIG. 5a. First, the operation of the control circuit will be explained.

Referring to FIG. 5a, reference numerals 30, 31 indicate differential comparators; 32 an AND circuit; 33 a NAND circuit; and 300, 301, 302, 310, 311, 312 indicate input resistors. The positive terminal of the differential comparator 30 receives the .x-axial component Ax, of the displacement applied through a terminal 304 and the absolute value MW of the y-axial component Ay, of the displacement applied through a terminal 303. While, the negative terminal of the comparator is connected to the ground potential. On the other hand, the negative terminal of the other differential comparator 31 receives the component Ax, applied through said terminal 304 and the negative absolute value 'l l/il of said y-axial component Ay, applied through a terminal3l4, and the positive terminal of said comparator 31 receives the ground potential. Each of the differential comparators 30, 31 operates in such a manner that it produces an output signal (this state is referred to as on-state") only when the potential at the positive terminal is not lower than the potential at the negative terminal. Thus, the comparator 30 becomes on-state when i Z l ll but assumes off-state when i l llil On the other hand. the comparator 31 assumes on-state when l i l yi but assumes otT-state if i i Mill The outputs of the comparators 30, 31 are applied to the AND-circuit 32 as inputs. Then, l will appear at the output terminal of the AND-circuit 32 if the input signals of the circuit fulfill the conditions of is C.

FIG. 6a shows the input-to-output characteristics of the differential comparator 30; FIG. 6b the same of the differential LII comparator 31; and FIG. 60 the overall input-to-output characteristics of the circuit including the AND-circuit 32 and NAN D-circuit 33.

Next, referring to FIG. 5b which shows an embodiment of the limiting-value-generating circuit controlled by the abovedescribed outputs C and G reference numerals 340, 390 indicate input terminals to which a predetermined input signal V is applied; 38, 39 potentiometers which generate coefficients Alli Ay;

Mail and 1m and 34, 35, 36 37 switches for selecting the limiting values for the limiters. The switches 34, 36 are controlled by the output of the NAND-circuit 33 of the above-described control circuit and select the limiting value when While, the switches 35, 37 are controlled by the output of the AND-circuit 32 to select the limiting value when i ii I/ii, then a signal is applied to the limiter l1 and V to the limiter 12.

The second example of the simplification of the limiting values relates to a case where View.

of the formulas (6) is approximated by 2" and the integer number m is selected so as to fulfill the following conditions:

That is, it is assumed that Lx,=2"'-V-Ax, and Ly 2""V-Ay,. This method relates to the normalization within the register on the basis of the largest one of Ax, and Ay, and this method is most suitable for digital systems. Assuming that the values of the coordinates (x, y) of a point under consideration are in a range indicated by fixed decimal points and by or that the full scales of the respective coordinates are respectively l, the following approximation made:

A233 All/ 2 (where, m is an integer number.) The integer number m is the maximum number which fulfills the following conditions:

0.5; max(2-IA-'i|, 'i yii) Then, Lx, and Ly, are simplified respectively as follows:

Lx =V-2"-At, and Ly,=V-2-Ay, In this case, the line-generating rate v varies in the range as indicated by 0.5 described. v /2 V, which is an allowable variation in practical use, The reasons why this method is most suitable to a digital system, is the fact that -l il or "'-l yr| can be obtained simply by shifting l il Min! to the left by m bits. A digital-type embodiment of the simplified limiting value generator will now be described Referring to FIG. 7, reference numerals 40, 41 indicate shift registers for storing Ax, and Ay,; 420, 422, 426, 44 AND circuits; 421, 423 NOT AND circuits; 43 a NAND circuit; and 424, 425 OR circuits. The AND-circuit 44 operates to shift the shift registers 40, 41 to the left. The NAND-circuit 43 operates at the end of the shift signal, to read out the contents of the shift registers 40, 41 in which digital signals corresponding to An, Ay, expressed with fixed decimal points are stored. It is assumed that the numerical value is expressed by a complement of two. x,, or y, is a sign bit and indicates 0" if Ax, or Ay, is positive, or l if it is negative. The decimal point is assumed to be put between .t', and x, as well as between y and y,.

In order to shift the shift registers 40, 41 by m bits to the left as mentioned above, it is only required to shift the contents of both registers to the left until at least either one of the two most significant bits x, and x, of the register 40 or the two most significant bits y, and y, of the register 41 becomes 0i or l0". Since the contents of the register are multiplied by 2 each time it is shifted to the left by one bit, repetition of this process m times, that is, the shift of m bits corresponds to a multiplication by 2'". Thus, at the end of the shift. the conditions of are attained.

It will be deduced from the above description that the conditions of the shift is the following logic:

The arrangement indicated by reference numeral 42 in FIG. 7 is an embodiment of the above logic. The output signal from the AND-circuit 426 thus represents the shift conditions, and a logic product of this signal and a clock signal supplied through a terminal 441 is applied from the AND-circuit 44 to the shift registers 40, 41 to shift said registers to the left sequentially. When two bits at the left end of at least one of the shift registers become different in sign from each other, the AND-circuit 426 closes the gate and the NAND-circuit 43 opens the gate. The output of the NAND-circuit 43 serves as a control signal to take out the contents of the shift registers 40, 41, which are 2""Ax, and 2"'-Ay, respectively.

Heretofore, circuits for determining the limiting values Lx Ly, have been described in connection with an analog system and a digital system. It will be understood that there are various other circuits for the same purpose.

FIG. 8 shows the x-axis part of an embodiment of theline generator according to this invention, which operates on a digital input .x, and a digital limiting value Lt,

In the figure, reference numerals 50, 70 and 90 indicate operating amplifiers which are included respectively in the integrator 5, sign changer 7 and adder 9; and numerals 10, ll 1, 112 digital-to-analog converters, said converter 10 being provided with a reference voltage V,, and providing the adder 9 with a current proportional to the digital input x,, that is, the xaxis component of the destination, and said converters llll. 112 serving as sources of electric currents which are supplied to the diode bridge-type limiter 11 to set its limiting value Numeral 8 indicates a finish-detecting circuit which detects and indicates the finish of the line generation when output 6,. of the adder 9 closely approaches the linear region of the limiter 111 (the region of as shown in FIG. 3a). The finish-detecting circuit 8 has a construction almost similar to that of the control circuit shown in FIG. 50. If, in FIG. a, the NAND-circuit 33 is removed, the input signal Ax, is substituted by the output 5, of the adder 9, and the inputs lAy l and lAy,l

are replaced by predetermined minute voltages V, and V. corresponding to 60/2 and /2, then the circuit of FIG. 5 will become substantially the same as the finish-detecting circuit 8 in FIG. 8. Therefore, the output from the finish-detecting circuit 8 will be I when i 92 respectively an input resistor and a feedback resistor of the adder 9; 71 and 72 an input resistor and a feedback resistor of the sign changer 7, said resistors 71 and 72 having the same value; and 52 an input resistor of the limiter 11. In FIG. 8, the requ red straight line is generated with the input signal fa l and the limiting value lLm l being given as the conditions for operation. This operation has been already described in connection with FIG. 2. Hereunder, explanation will be given concerning the limiter II consisting of the diode bridge circuit 110.

As shown in FIG. 8, the input terminal of the diode bridge circuit 110 is connected to the adder 9 through the resistor 52, and the output of the bridge circuit 110 is connected to the integrator 5. Further, the control terminals of the bridge circuit 110 which are equivalent to the plate (anode) P and the cathode K, are connected to the digital-to-analog converters 112 and 1111 respectively. The converters 112, 111 are provided with reference voltages V,, and --V,, whose polarities are in conformity with the conducting direction of the bridge 110. The reference voltages are similar to those which are usually provided in the digital-analog converters and serve as sources for supplying electric current to an outer circuit (in this case, the diode bridge circuit 110). The diode bridge circuit 110 includes diodes 11,, d d d, which are connected in the same direction.

Assuming that all of the four diodes have substantially the same characteristics and that the threshold voltage of the diodes is V, and the forward resistance is R,,, the input of the integrator 5 is zero when there exists no limiting value signal and no output signal from the adder 9. Even if the limiting value signal LA", is applied, the bridge circuit 110 will still be nonconductive if the voltage between the anode and the cathode is not sufficiently high to make the diode bridge 110 conductive. Such a state will not occur except when the line generator is not in operation, or in a rare case where the x-axis component of the required displacement is so small as to be negligible. Therefore, it is supposed in the following description that the limiting value is high enough to make the diode bridge conductive and the input signal 5, is in the limiting value region. Now, assuming that the voltages at the anode P and the cathode K are respectively V, and V when the limiting value is the electric current ld flowing through the diodes d, and d or d, and :1, will be as follows:

l,,=V,,/R,, In such a conducting state of the bridge circuit, the potential V, at the input terminal I of the bridge circuit due to the current 1,, is expressed as V V VQ. whereupon, if the digital input signal x, is fed through the input terminal I, it is applied as input to the adder 9 through the D-A converter 10, where the signal is converted to a corresponding output voltage 6,. which is applied to the input terminal I of the bridge circuit 110. Therefore, the operating region of the limiter III is determined as follows depending on the difference between the output voltage 2, of the adder f9 and the voltage V, at the tenninal I of the bridge circuit 110:

a. When e, IQ-V,

As the input voltage is imposed in such direction as to inhibit the current I,, flowing through the diode d,, said diode d, assumes a cutoff state, thereby the diode :1 too assuming cutoff" state, while the diodes d and d, maintain the "on" state. Accordingly, the limiting value detennined by the D-A converter I12 appears at the output terminal Q of the bridge 110 to become the input signal of the integrator. Thus, in this state, the input voltage of the integrator 5 is always maintained at the limiting value L275 and the limiter 11 operates in the limiting region.

All of the diodes d,-d, are conducting in this state, which is equivalent to the state in which the input and output terminals l and Q of the bridge 110 are directly connected. Therefore, the input voltage e, of the bridge 110 is applied to the input terminal of the integrator 5 without any change. That is, the limiter operates in the linear region.

The conducting state of the diode entirely opposite to that in the case of the above paragraph (a). That is, the diodes d and d, are made to assume the "cutofi' state while d, and d maintain "on" state. Therefore, the voltage determined by the D-A converter 11] appears at the output terminal 0 to become the input signal of the integrator 5. This state corresponds to the operation in the limiting region.

As is clear from the above description of the three states of operation, the limiter 11 operates in the linear region if e, V V, or in the limiting region if 6,; V,-V,Though the limiter rarely starts the operation in the linear region with a particularly small input signal, generally the operation is initiated in the limiting region and moves to the linear region.

It will be understood that the limiter II shown in FIG. 8 is only an example, and that the diode bridge circuit 110 may be replaced by transistors or other electric elements.

The above-described digital system is effective as a simple line generator which is applicable to cathode-ray tube display devices, drafting machines, electron beam processing apparatuses, tool machines and the likes, in which digital systems are usually employed to write the values entered from outside according to a desired pattern. A digital writing system which is considerably higher in writing speed than a corresponding analog system, is indispensable for the devices which require bridge I10 in this case is high-speed line generation or high-speed generation of an electron beam. In such devices, the use of the digital system as described above for generating a line from written data will be advantageous because of the simplicity of the device and the high speed of its operation.

What we claim is:

1. Apparatus for generating x and y coordinate analog signals of a rectilinear curve portion having a starting point whose coordinates are x and y,-,,;-, and an end point whose coordinates are x, and y, comprising:

an x coordinate integrator and a y coordinate integrator each having input and output terminals;

an x coordinate limiter having first and second input terminals and an output terminal connected to the input terminal of said x coordinate integrator;

a y coordinate limiter having first and second input terminals and an output terminal connected to the input terminal of said y coordinate integrator;

an x coordinate input terminal supplied with a signal representing the value x of the starting point which is changed to a signal representing the value x, of the end point when the rectilinear curve position is to be generated;

a y coordinate input terminal supplied with a signal representing the value y,.-,,;- of the starting point which is changed to a signal representing the value y, of the end point when the rectilinear curve portion is to be generated;

x coordinate differential means for producing an .r coordinate error signal which is the difference between a signal appearing at the output terminal of said .r coordinate integrator and a signal supplied to said x coordinate input terminal;

y coordinate difierential means for producing a y coordinate error signal which is the difference between a signal appearing at the output terminal of said y coordinate integrator and a signal supplied to said y coordinate input terminal;

means for supplying the .r and y error signals to the first input terminals of the respective corresponding limiters; and

control means for producing .r and y control signals of constant values and supplying the x and y control signals respectively to the second input terminals of the respective corresponding limiters, said limiters operatively supplying to the output terminals thereof respectively the error signals when the error signals are within a predetermined threshold range and the .r and y control signals when the error signals are out of the predetermined threshold range.

2. Apparatus according to claim 1, wherein said control means comprises means for producing an x-control signal representative of i i1) i i-1) (yi yi-1) and a y-control signal representative of '(yi' yil) i i-i) (yi' 'yi-l) where V represents a constant line-generating velocity, whereby a line-generating velocity of the rectilinear curve portion between the starting and end points is retained within a range from Vto VJ? 3. Apparatus according to claim 2, wherein said control means comprises:

means for generating an .r difference signal Ax; representing the difference of the x coordinate of the starting point from that of the end point and a y difference signal Ay, representing the difference of the y coordinate of the starting point from that of the end point;

an x coordinate square circuit for performing a square operation of the .r difference signal;

a y coordinate square circuit for performing a square operation of the y difference signal;

an adder for adding outputs of said x and y square circuits;

a square root function circuit for producing a square root of the output of said adder;

an x coordinate divider for operating division of the x difference signal by the output of said square root function circuit;

a y coordinate divider for operating division of the y difference signal by the output of said square root function circuit; and

means for multiplying the outputs of the respective dividers by a constant value V, respectively, to thereby obtain the x and y control signals.

4. Apparatus according to claim 1, wherein said control means comprises:

means for generating an .r difference signal Ax, representing the subtractions x,.r,-,,.;-

means for detecting whether an absolute value of the x difference signal Ax, is larger than an absolute value of the y difference signal Ay, or not; means for selectively generating as the .r control signal either a constant value V representing a constant linegenerating velocity or a value VAz MW in response to the detection by said detecting means whether the signals Ar, is larger than the signal in response to the detection by said detecting means or the constant value whether the signal is larger than the signal Z/ii or not.

5. Apparatus according to claim 1, wherein said control means comprises means to produce an .r control signal representative of V "2""(.r,x,- and a y control signal representative of V-2"'-(y,y,-, where m satisfies 0.5 max 6. Apparatus according to claim 4, wherein said control means further comprises a first and second differential amplifier, each having a pair of input terminals and an output terminal, one terminal of each pair being connected to a source of common reference potential, while the other respective terminals of said first and second differential amplifiers are connected to receive said Ar, difference signal from said x diffcrence-signal-generating means, and further including a first AND gate connected to the output of each of said differential amplifiers and an AND gate correspondingly connected to each of the outputs of said difi'erential amplifier.

7. An apparatus in a accordance with claim 5, wherein said control means includes a pair of shift registers, one for the x component and one for the y component, and wherein two adjacent stages of each of said shift registers are connected to a logic circuit, said logic circuit comprising a first and second pair of respective AND and NAND gates for receiving the outputs from the respective two adjacent stages of said register, and a pair of OR circuits for combining the outputs of the AND and NAND gates associated with each respective stage, and an output AND for receiving the outputs of said OR gates, and further including an additional AND gate connected in parallel with said output AND gate for taking out the contents of said register.

8. An apparatus in accordance with claim 1, wherein each of said coordinate limiters comprises a diode bridge, two terminals of which are connected between a corresponding differential means and integrator, while the other two terminals of said diode bridge are coupled to said control means.

9. An apparatus in accordance with claim 8, further including a finish detector circuit, for indicating the finish of a line generation, said finish-detecting circuit comprising a first and second differential amplifier, each having a pair of input terminals and an output terminal, one terminal of each of said pair being connected to a source of common reference potential, while the other respective terminals of said first and second differential amplifiers are connected to receive said Ax, difference signal from said x difference signal-generating means, and further including a first AND gate connected to the output of each of said differential amplifiers and a NAND gate correspondingly connected to each of the outputs of said differential amplifiers.

7 t l t l 

1. Apparatus for generating x and y coordinate analog signals of a rectilinear curve portion having a starting point whose coordinates are xi 1 and yi 1 and an end point whose coordinates are xi and yi comprising: an x coordinate integrator and a y coordinate integrator each having input and output terminals; an x coordinate limiter having first and second input terminals and an output terminal connected to the input terminal of said x coordinate integrator; a y coordinate limiter having first and second input terminals and an output terminal connected to the input terminal of said y coordinate integrator; an x coordinate input terminal supplied with a signal representing the value xi 1 of the starting point which is changed to a signal representing the value xi of the end point when the rectilinear curve position is to be generated; a y coordinate input terminal supplied with a signal representing the value yi 1 of the starting point which is changed to a signal representing the value yi of the end point when the rectilinear curve portion is to be generated; x coordinate differential means for producing an x coordinate error signal which is the difference between a signal appearing at the output terminal of said x coordinate integrator and a signal supplied to said x coordinate input terminal; y coordinate differential means for producing a y coordinate error signal which is the difference between a signal appearing at the output terminal of said y coordinate integrator and a signal supplied to said y coordinate input terminal; means for supplying the x and y error signals to the first input terminals of the respective corresponding limiters; and control means for producing x and y control signals of constant values and supplying the x and y control signals respectively to the second input terminals of the respective corresponding limiters, said limiters operatively supplying to the output terminals thereof respectively the error signals when the error signals are within a predetermined threshold range and the x and y control signals when the error signals are out of the predetermined threshold range.
 2. Apparatus according to claim 1, wherein said control means comprises means for producing an x-control signal representative of and a y-control signal representative of where V represents a constant line-generating velocity, whereby a line-generating velocity of the rectilinear curve portion between the starting and end points is retained within a range from V to V
 2. 3. Apparatus according to claim 2, wherein said control means comprises: means for generating an x difference signal Delta xi representing the difference of the x coordinate of the starting point from that of the end point and a y difference signal Delta yi representing the difference of the y coordinate of the starting point from that of the end point; an x coordinate square circuit for performing a square operation of the x difference signal; a y coordinate square circuit for performing a square operation of the y difference signal; an adder for adding outputs of said x and y square circuits; a square root function circuit for producing a square root of the output of said adder; an x coordinate divider for operating division of the x difference signal by the output of said square root function circuit; a y coordinate divider for operating divisioN of the y difference signal by the output of said square root function circuit; and means for multiplying the outputs of the respective dividers by a constant value V, respectively, to thereby obtain the x and y control signals.
 4. Apparatus according to claim 1, wherein said control means comprises: means for generating an x difference signal Delta xi representing the subtractions xi-xi 1; means for detecting whether an absolute value of the x difference signal Delta xi is larger than an absolute value of the y difference signal Delta yi or not; means for selectively generating as the x control signal either a constant value V representing a constant line-generating velocity or a value in response to the detection by said detecting means whether the signals Delta xi is larger than the signal or not; and means for selectively generating as the y control signal either a value in response to the detection by said detecting means or the constant value whether the signal is larger than the signal or not.
 5. Apparatus according to claim 1, wherein said control means comprises means to produce an x control signal representative of V52 .2m.(xi-xi 1) and a y control signal representative of V.2m.(yi-yi 1) where m satisfies 0.5 max
 6. Apparatus according to claim 4, wherein said control means further comprises a first and second differential amplifier, each having a pair of input terminals and an output terminal, one terminal of each pair being connected to a source of common reference potential, while the other respective terminals of said first and second differential amplifiers are connected to receive said Delta xi difference signal from said x difference-signal-generating means, and further including a first AND gate connected to the output of each of said differential amplifiers and an AND gate correspondingly connected to each of the outputs of said differential amplifier.
 7. An apparatus in a accordance with claim 5, wherein said control means includes a pair of shift registers, one for the x component and one for the y component, and wherein two adjacent stages of each of said shift registers are connected to a logic circuit, said logic circuit comprising a first and second pair of respective AND and NAND gates for receiving the outputs from the respective two adjacent stages of said register, and a pair of OR circuits for combining the outputs of the AND and NAND gates associated with each respective stage, and an output AND for receiving the outputs of said OR gates, and further including an additional AND gate connected in parallel with said output AND gate for taking out the contents of said register.
 8. An apparatus in accordance with claim 1, wherein each of said coordinate limiters comprises a diode bridge, two terminals of which are connected between a corresponding differential means and integrator, while the other two terminals of said diode bridge are coupled to said control means.
 9. An apparatus in accordance with claim 8, further including a finish detector circuit, for indicating the finish of a line generation, said finish-detecting circuit comprising a first and second differential amplifier, each having a pair of input terminals and an output terminal, one terminal of each of said pair being connected to a source of common reference potential, while the other respective terminals of said first and second differential amplifiers are connected to receive said Delta xi difference signal from said x difference signal-generating means, and further including a First AND gate connected to the output of each of said differential amplifiers and a NAND gate correspondingly connected to each of the outputs of said differential amplifiers. 